The subject matter disclosed herein relates generally to integrated circuits. More specifically, the disclosure provided herein relates to spare latch distribution for an integrated circuit design.
Typically, design changes come up in the final phase of the circuit design, which need to be implemented without affecting the processed sections. These changes are conventionally known as an engineering change order (ECO). In order to satisfy the need to implement these ECOs, spare circuitry is normally included in the circuit design. Spare latches are an example of this spare circuitry and are often used to implement the ECOs.
During the initial design phase, spare latches are not part of the data path, and so, latch clustering and placement give the spare latches the least priority. This leads to all spare latches to be pushed to the least dense region of the circuit. However, if the ECO is needed to adjust for timing issues, if the spare latch is not physically in close proximity to the region of the circuit that needs to utilize the spare latch, additional timing delays can accrue due to the distance between the latch and the region of the circuit.